Semiconductor structures comprising three-dimensional arrays of chips have emerged as an important packaging approach. A typical three-dimensional electronic structure consists of multiple integrated circuit chips having main planar surfaces adhesively secured together to form a monolithic structure (referred to herein as a "stack" or "cube"). Two common types of semiconductor chip stacks are the vertically-extending (or "pancake") stack and the horizontally-extending (or "breadloaf") stack. A metallization pattern is often provided directly on one (or more) edge surface(s) of the multichip stack for interconnecting the semiconductor chips and for electrical connection of the stack to external circuitry. This metallization pattern can include both individual electrical connects and bused electrical connects.
At least one redundant chip is often provided in the multichip semiconductor stack so that if one of the primary chips in the stack should fail following stack fabrication and/or stressing (i.e., burn-in), the redundant chip may be "invoked" to provide the electronic circuit package with the desired performance level. This activity is referred to in the art as "sparing." A preferred technique for providing programmable sparing capability to a multichip package, either with or without the inclusion of a spare chip in the multichip package, is set forth in commonly assigned, U.S. Pat. No. 5,502,333 and entitled "Semiconductor Stack Structures and Fabrication/Sparing Methods Utilizing Programmable Spare Circuit."
Conventional testing of a multichip semiconductor structure involves individual testing of the semiconductor device chips in the stack prior to burn-in stressing of the stack. If a short circuit is encountered, then the effected chip, or a portion thereof, is isolated. Thereafter, burn-in stressing and testing of the multichip semiconductor stack is performed, during which time further semiconductor device chip short circuits may occur. Should this happen, the burn-in process must be discontinued. The failed circuitry must then be isolated and disconnected, afterwhich the burn-in process can be reinitiated. Obviously, this entire process can be time consuming and labor intensive. Conceivably, iterative burn-in stressing and isolation of defective circuits within the multichip stack might occur using this approach.
The isolation of shorted chips is required because a short circuit defect on one semiconductor device chip in the multichip stack can effect burn-in stressing of other semiconductor device chips in the stack. For example, a short circuit on a power plane of a semiconductor device chip in the stack can actually lower the voltage level being applied to adjacent semiconductor device chips, thereby potentially defeating burn-in stressing/testing conditions on these adjacent chips, i.e., unless the above-described iterative process is followed.
Burn-in stressing and testing of a multichip semiconductor structure is most effective after final operational interchip wiring has been formed. However, repair of a multichip stack after final wiring has been added is difficult. For example, if an input/output transfer wire shorts to ground it is nearly impossible to repair. Since multichip stack fabrication costs can be significant, a repair technique subsequent to final wiring would be a significant factor in insuring the feasibility of high density electronic circuit packaging.
Based upon the above, there remains a need in the art for an enhanced multichip semiconductor structure which requires only a single burn-in stressing and testing cycle, and which is readily rewirable notwithstanding the existence of final interchip connections.